1. Field of the Invention
This invention relates to capacitors and, more particularly, to capacitors suitable for inclusion in integrated circuits such as dynamic memories.
2. Description of the Prior Art
The great increase in computing power of computers of all types in recent years has necessitated an increase in the amount of memory which can be rapidly accessed by a central processing unit. This, in turn, has led to a continuing interest in providing greater amounts of storage on a single chip and the reduction of the size of memory cells.
Memory technology may be considered as divided into two types, each of which has some advantages relative to the other for certain requirements of any computing system. Static memories generally rely on a bistable active circuit for the storage of individual bits of data. Static memory cells generally have a substantial number of active devices, such as transistors and are relatively large, limiting the number of memory cells which may be formed on a single chip. Nevertheless, the storage provided is stable and no refresh of data is required. Therefore, the memory can be accessed at any time, enhancing the extremely fast read or write time of this type of memory.
In contrast, dynamic memories require far fewer electronic components in each memory cell and far greater numbers of cells may be placed on a single chip. However, unlike the stable data storage provided by static memories, in dynamic memories, data is typically stored as charge on a capacitor within the storage cell. The capacitors are subject to leakage and, therefore, the charge must be periodically refreshed or rewritten to avoid corruption of data.
Perhaps the largest component of a dynamic memory cell is the capacitor in which charge is stored. Since the primary virtue of dynamic memories is the possibility of reducing memory cell size to increase the number of memory cells which can be formed on a single chip, there has been much interest in reducing the "footprint" or area of the substrate or chip required for formation of each capacitor. Much of the effort, in this regard, has focussed on the improvement of sense amplifier structures to reduce the amount of charge which must be stored, at a relatively low voltage, in each capacitor. At the present state of the art, data can often be reliably stored by storing perhaps only a few dozen electrons in each capacitor. Storage of such small amounts of charge makes charge leakage of each capacitor particularly critical since each electron lost to capacitor leakage represents a correspondingly larger portion of the voltage which must be detected by sense amplifiers in the memory.
Such improvements in sense amplifier structures has been accompanied by numerous capacitor designs to reduce the "footprint" of the capacitor on the chip. So-called trench capacitors which are formed vertically within the semiconductor substrate have been a particularly significant development in this regard. However, the depth within the substrate to which trench capacitors may be reliably extended is limited and further reductions in capacitor "footprint" area are, at the present state of the art, usually accompanied by reduction of the charge storage capacity of each capacitor.
As process complexity has increased in an effort to increase trench depth in order to increase the ratio of charge storage capacity to chip area required for a capacitor, manufacturing yields have been adversely affected, further increasing production costs. At the same time, such complexity and miniaturization has tended to increase the resistance of contacts to the capacitor structure, reducing access speed, operational reliability and noise margins. These same increases in process complexity have also led to problems of increased susceptibility to charge leakage which, as pointed out above, is particularly critical at extreme integration densities and the small amounts of charge which may be stored at low voltages.
Further, as an incident of memory design, the minimum charge storage capacity of each memory capacitor must be kept at least comparable to the parasitic capacitance of wiring connections on the chip which are required to provide access to each cell. Thus, as dynamic memory designs have sought to exceed 256 megabytes, requiring relatively long bit and word lines, it has been difficult to reconcile the competing design requirements of reduction of capacitor "footprint" area with the need to maintain a charge storage capacity which will allow reasonable refresh rates and adequate operating margins relative to parasitic capacitance of chip wiring necessary to access such large numbers of memory cells.